1. Field of the Invention
The present invention relates to a method of forming a rerouting pattern by plating on a semiconductor wafer.
2. Description of the Related Art
In a semiconductor product, for example, a Super Chip-Size Package (Super CSP) product, conductive posts (for example, copper posts) or rerouting patterns are formed by plating on a surface of a semiconductor chip cut out from a semiconductor wafer. Also, in the process of forming a semiconductor product having bumps, the conductive posts or the rerouting patterns are formed. Prior to the plating treatment, plating electrodes (electric power feeding layer) are formed on the semiconductor wafer.
For example, Japanese Laid Open Patent Application No. 2003-031768 (page 5, and FIG. 1) discloses background art of this technology.
FIG. 1 through FIG. 6 illustrate the process of forming rerouting patterns in the related art.
FIG. 1 is a top view of a semiconductor substrate.
FIG. 2 is a cross-sectional view of the semiconductor substrate in FIG. 1 along the line AA′.
In step one, a conductive layer is formed. Specifically, as illustrated in FIG. 1 and FIG. 2, a conductive layer 610 is formed on a semiconductor wafer 600 by sputtering. Alternatively, an insulating layer formed from polyimide or epoxy may be disposed on the semiconductor wafer 600, and the conductive layer 610 may be deposited on the insulating layer.
FIG. 3 is a top view of the semiconductor substrate for explaining the process of forming rerouting patterns continued from FIG. 1.
FIG. 4 is a cross-sectional view of the semiconductor substrate in FIG. 3 along the line AA′.
In step two, a resist layer is formed. Specifically, as illustrated in FIG. 3 and FIG. 4, a negative resist layer 620 is formed on the conductive layer 610. Further, after the step two and before a subsequent step three (described below), a protection film (not illustrated) is disposed on the resist layer 620 to protect the resist layer 620. Here, the resist layer 620 may be either a negative one or a positive one. Below, it is assumed that the resist layer 620 is a negative resist layer.
FIG. 5 is a top view of the semiconductor substrate for explaining the process of forming rerouting patterns continued from FIG. 3.
In step three, exposure is carried out. Specifically, as illustrated in FIG. 5, a reticle pattern (not illustrated) is disposed at a specified position above the negative resist layer 620, and a projection lithography stepper (not illustrated) emits ultraviolet rays onto the negative resist layer 620 through the reticle pattern to expose the negative resist layer 620. After that, the protection film on the negative resist layer 620 is removed.
In the grid area shown in FIG. 5, each cell 700 indicates an area exposed by the projection lithography stepper at one time (referred to as “unit exposure area” below). The projection lithography stepper exposes the cells 700 one by one by using a reticle having a reticle pattern corresponding to the shape of the plating electrodes to be formed (plating pattern).
FIG. 6 is an enlarged perspective view of the semiconductor substrate for explaining the process of forming rerouting patterns continued from FIG. 5. In FIG. 6, developing is executed on the semiconductor substrate after the exposure step as shown in FIG. 5.
As illustrated in FIG. 6, the conductive layer 610 is formed on the semiconductor wafer 600, and the resist layer 620 (dotted portion) is formed on the conductive layer 610.
Because of the exposure step and the developing step, plating patterns (rerouting patterns) 650 are formed in the resist layer 620. In this example, because the resist layer 620 is a negative resist layer, the exposed portions of the resist layer 620 become insoluble or hardly soluble in the developing solution, and the un-exposed portions are removed by developing, resulting in the plating patterns 650. At the position where the plating patterns 650 are formed, the conductive layer 610 is exposed.
After the semiconductor wafer 600 having the plating patterns 650 is mounted on a plating jig, as disclosed in Japanese Laid-Open Patent Application No. 8-170198 (FIG. 1 and FIG. 2), and Japanese Laid-Open Patent Application No. 11-204459 (FIG. 1), the semiconductor wafer 600 is immersed into a plating tank filled with a plating solution and is plated by electro-plating (for example, copper plating). In this process, sealing rubber is arranged in the plating jig, and the sealing rubber is disposed on the periphery of the semiconductor wafer 600 to be liquid-tight. In this way, the plating solution only contacts the plating position of the semiconductor wafer 600, and does not leak out to the back side of the semiconductor wafer 600.
In the above plating process, a specified conductive metal material (for example, copper) is plated in the plating patterns 650; thereby, rerouting patterns are formed in the plating patterns 650. Next, the negative resist layer 620 is removed, and rerouting patterns corresponding to the plating patterns 650 are formed on the semiconductor wafer 600.
Recently, in order to improve electrical characteristics of the rerouting patterns, it has been proposed to increase the thickness of the rerouting pattern formed on the semiconductor wafer 600. In the related art, the resist layer is formed by coating a negative to a positive liquid resist. However, with this method, only a thin resist layer less than 10 μm can be formed, and it is difficult to increase the thickness of the rerouting pattern. For this reason, recently, it has been proposed to use a dry film resist (DFR) to increase the thickness of the rerouting pattern.
However, when a dry film resist thicker than 10 μm is used in the above plating process, even when the sealing rubber is used, it is difficult to prevent leakage of the plating solution, and the plating solution leaks out to the periphery and the back side of the semiconductor wafer 600.
FIG. 7 is an enlarged perspective view of the semiconductor substrate mounted on a plating jig. For convenience of illustration and explanation, only a sealing rubber 635 of the plating jig is shown in FIG. 7.
In FIG. 7, the plating solution contacts the inner side of the sealing rubber 635, and the sealing rubber 635 is arranged so that the plating solution does not leak out to the outside of the sealing rubber 635.
Nevertheless, as described with reference to FIG. 5, in the step of exposure, the cells 700 of the semiconductor wafer 600 are exposes one by one using a reticle. In the process, at the edge of the semiconductor wafer 600, the cells 700 extend out of the semiconductor wafer 600; as a result, these patterns of the reticle cannot be exposed.
Focusing on the edge of the semiconductor wafer 600 in FIG. 7, a groove-like plating pattern 650 at the edge of the semiconductor wafer 600 is in communication with outside through a communication portion 651, in other words, an opening is present on the side surface of the negative or positive resist layer 620. Consequently, in the plating step, the plating solution flows into the communication portion 651 from the inner side 652 of the plating pattern 650, and due to this, in spite of the presence of the sealing rubber 635, the plating solution leaks out to the outside of the sealing rubber 635.
Meanwhile, with a thin negative or positive resist layer 620 (for example, less than 10 μm), when the sealing rubber 635 is pressed on the resist layer 620, the resist layer 620 bends because the resist layer 620 is made from a flexible resin. In addition, when the sealing rubber 635 seals the resist layer 620, the capillary phenomenon occurs, and the sealing rubber 635 is elastically deformed when entering the plating pattern 650. Due to these facts, plating solution leakage does not occur when the resist layer 620 is thin.